1. Field of the Invention
The present invention relates to an instruction control method for controlling the execution of instructions in a processor in which the frequency of an internal clock signal differs from the frequency of an external clock signal by which input and output data are synchronized, and to an instruction control apparatus for implementing the instruction control method,
2. Description of Background
Conventionally, large scale integrated circuit processors controlled by machine instruction are well known. Recently, because the calculation speed in the processor has been improved as transistors are largely integrated in the processor, the frequency of an internal clock signal by which micro instructions are synchronized in an integrated circuit has been increased. For example, the frequency of the internal clock signal has reached tens of millions and a further increase in the frequency is expected in the future.
However, a board attached the integrated circuits is comparatively large although the circuits are miniaturized. Therefore, a load capacitance such as the electric capacitance of a condenser arranged on the board remains large. In other words, data signals which are synchronized with external clock signals are transmitted among the integrated circuits at a low speed in the board. Therefore, the difference in the transmission speed of the data signals between the outside of the integrated circuit and the integrated circuit has increased as the integrated circuit is miniaturized.
In cases where the circuit is not largely integrated, the difference in the transmission speed of the data signals between the outside of the integrated circuit and the integrated circuit is comparatively small so that the external clock signal utilized outside the integrated circuits is provided to the integrated circuits to be utilized as the internal clock signal without shifting the frequency of this external clock signal. In other words, the data signals in the integrated circuits and those outside the circuits are synchronized with the same clock signal.
However, the circuit has been miniaturized and largely integrated so that the data signals in the integrated circuit are transmitted at high speed. Therefore, the data signals can be synchronized with a high frequency clock signal with a higher frequency than that of the external clock signal transmitted among the integrated circuits in the board. Accordingly, it is impractical to synchronize the data signals in the integrated circuits and those outside the circuits with the same clock signal.
To solve the above drawback, a clock system 11 shown in FIG. 1 has recently been utilized.
FIG. 1 is a block diagram of an integrated circuit operating in synchronization with high and low frequency clock signals. The high frequency clock signal is utilized as the internal clock signal and the low frequency clock signal is utilized as the external clock signal.
As shown in FIG. 1, an integrated circuit 11 comprises an integrated internal circuit 12 in which internal signals synchronized with the high frequency clock signal are transmitted and an input/output circuit 13 for providing an input signal provided from outside the integrated internal circuit 12 to the circuit 12 in synchronization with the low frequency clock signal, and for providing an output signal transmitted from the integrated internal circuit 12 to the outside in synchronization with the low frequency clock signal.
In the above configuration, the transference of the input and output signals between the integrated internal circuit 12 and outside the circuit 12 is accomplished while the input and output signals are synchronized with the low frequency clock signal. On the other hand, the operation in the integrated internal circuit 12 is executed while the internal signals are synchronized with the high frequency clock signal.
Therefore, two types of clock signals must be provided to the clock system 11 from outside the integrated internal circuit 12, so that a troublesome wiring design such as a so-called emitter complete logic is required to provide a wire for the high frequency clock signal.
To solve the above drawback, another integrated circuit 21 shown in FIG. 2 has been utilized.
FIG. 2 is a block diagram of the integrated circuit 21 provided with a phase locked loop.
As shown in FIG. 2, the integrated circuit 21 comprises a phase locked loop 22 for generating a high frequency clock signal of which the phase is locked by a low frequency clock signal provided from outside the integrated circuit 21, an integrated internal circuit 23 in which internal signals are transmitted in synchronization with the high frequency clock signal generated in the phase locked loop 22, and the input/output circuit 13.
In the above configuration, because the high frequency clock signal is generated in the phase locked loop 22, a wire transmitting the high frequency clock signal to the outside of the integrated circuit 21 is not required, so that the wiring design of the board is simplified.
However, there are drawbacks in the integrated circuits 11, 21 in cases where a signal synchronized with the high frequency clock signal are output through the input/output circuit 13 in which the signal must be synchronized with the low frequency clock signal.
To describe the drawbacks with reference to FIGS. 3, 4, the frequency of the high frequency clock signal is considered to be four times as large as that of the low frequency clock signal.
FIG. 3 is a block diagram of an integrated circuit 31 typically showing the integrated circuits 11, 21.
External signals are transferred between an integrated internal circuit 32 and the outside of the circuit 32 through an input/output circuit 33.
FIG. 4 is a timing chart showing the phase of the slow frequency clock signal during the execution of an instruction executed in synchronization with the high frequency clock signal, the instruction being executed in the integrated internal circuit 82 shown in FIG. 3.
As shown in FIG. 4, instructions stored in a instruction memory (not shown) of the integrated internal circuit 32 are executed when the high frequency clock signal is at a leading edge thereof, while input/output operation is executed in the input/output circuit 33 when the low frequency clock signal is at a leading edge thereof.
An output operation will first be described. In cases where an instruction for providing output data to the outside of the integrated internal circuit 82 is executed in an execution period of time T.sub.12, T.sub.23, or T.sub.34, the output data promptly appears on an interface signal wire 34 disposed between the integrated internal circuit 32 and the input/output circuit 33. However, because the appearance time of the output data does not agree with the leading edge of the low frequency clock signal at a first cycle (1) of the low frequency clock signal, the output data is abandoned without being received in a flip-flop 35 of the input/output circuit 33. On the other hand, in cases where the output instruction is executed in an execution period of time T.sub.45, the output data promptly appearing on the interface signal wire 84 is provided to the outside of the integrated internal circuit 82 through the flip-flop 85 and an external signal wire 36 at a second cycle (2) of the low frequency clock signal because the appearance of the output data agrees with the leading edge of the low frequency clock signal at a time T.sub.5.
Therefore, the output data can be provided to the outside only when the output instruction is executed in a specific execution time period such as the period T.sub.45.
An input operation will next be described. In cases where an instruction for receiving input data from outside the integrated internal circuit 32 is executed in an execution time period T.sub.56, the first input data appearing on the interface signal wire 34 at the first cycle (1) of the low frequency clock signal is provided to the integrated internal circuit 32 through an internal signal wire 37. On the other hand, in cases where the input instruction is executed in execution time periods T.sub.67, T.sub.78, or T.sub.89, the second input data appearing on the interface signal wire 34 at the second cycle (2) of the low frequency clock signal is provided to the integrated internal circuit 32 through the internal signal wire 37.
Therefore, the input data cannot be specified because either the first or second input data is provided to the circuit 32 according to the execution time.
That is, in cases where the phase of the slow frequency clock signal in a first execution time differs from that in a second execution time, one operation executed in the first execution time differs from another operation executed in the second execution time regardless of the execution of the same instruction in the input or output operation.
In the above case, the operation expected by a programmer can be executed in cases where the phase of the slow frequency clock signal at an execution time of a top instruction first executed in a program including input and output instructions can be expected, and the program is drawn up while counting the number of execution steps for all instructions. However, in cases where the program is utilized many times as a subroutine in a large main program, the programmer cannot predict the phase of the slow frequency clock signal when the top instruction in the program is executed. Therefore, the operations of the input and output instructions differ from the operations expected by the programmer.
Moreover, in cases where the high frequency clock signal is generated by the phase locked loop 22 as shown in FIG. 2, because a lead-in time corresponding to the necessary time for generating the high frequency clock signal in the phase locked loop depends on the frequencies of both the high and low frequency clock signals, the leadin time is not constant. Therefore, after the phase locked loop is reset, the time required to generate the high frequency clock signal and to operate the program is shifted.
Accordingly, it is difficult to know the phase of the low frequency clock system when the top instruction in the program is executed. That is, the operation expected by the programmer cannot be substantially implemented.